ATMEGA324A-MCHR【PDF 30/160 页】IC MCU AVR 32K 20MHZ 44QFN

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125

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNTn)

increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)

is cleared.

Figure 16-6. CTC mode, timing diagram.

An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the

interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-

ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a

low prescaler value must be done with care since the CTC mode does not have the double buff-

ering feature. If the new value written to OCRnA or ICRn is lower than the current value of

TCNTn, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.

For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-

quency of f

OCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is

defined by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

16.10.3

Fast PWM mode

The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared

on the compare match between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare

Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope

operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor-

TCNTn

OCnA

(Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

Period

(COMnA1:0 = 1)

OCnA

clk_I/O

2 N

OCRnA

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